1. Field of the Invention
The present invention relates to a die package structure and a related die package structure manufacturing method, and particularly relates to a die package structure utilizing a TSV structure and a related die package structure manufacturing method.
2. Description of the Prior Art
High speed and high density structure are desired for current DRAM technique. In order to meet the requirement of a high density structure, a 3D package technique is developed. Comparing with the traditional 2D package technique, the chip utilizing the 3D package technique has a vertically-conductive structure. Such that the chip can have a shorter conductive path and less signal delay time than a chip utilizing the traditional 2D package technique. Besides, chip performance can increase via such structure. Also, chip power consumption, parasitic capacitance and conductance can decrease as well.
TSV (Through-Silicon Via) technique is one kind of 3D package technique. However, current TSV technique is still unstable and has high cost such that current TSV technique is hard to compete with traditional package technique.